There is a growing need for fault tolerant circuits as integrated circuit (IC) process feature sizes become smaller. Smaller transistor feature sizes carry the advantages of higher speed and greater density, however reduced tolerance to Single Event Upsets (SEUs) due to radiation and possibly other noise sources is becoming a recognized problem. Radiation can have detrimental effects on electronics, including immediate temporary information upset and increased power consumption as a circuit responds to a SEU. Ionizing radiation occurs in the form of charged particles that possess enough energy to break atomic bonds and create electron/hole pairs in the absorbing material. Such particles may include protons, electrons, atomic ions, and photons with energies greater than the material band gaps. The primary ionizing radiation effects on microelectronics can be categorized as either total ionizing dose (TID) effects or transient effects. TID effects are a function of ionizing radiation accumulation over months or even years, which can lead to performance degradation and functional failure. Transient radiation effects are primarily the result of photo-currents generated as energetic particles pass through the circuit. The SEU occurs when the charge collected as a result of the generated photo currents is of sufficient magnitude to alter the logic state of a susceptible node. An upset node may further cause the alteration of the contents of circuit memory elements or alter the operation of the circuit in such a way to cause an error in a logic function. The SEU problem is especially pronounced in space electronics and to a lesser degree in aircraft electronics. As IC process feature sizes continue to decrease in size, it is possible that terrestrial electronic problems will become more evident, especially at higher elevations.
Conventional Radiation Hard By Design (RHBD) electronic technologies are acceptable for feature sizes greater than 200 nm. This RHBD technology has focused mostly on layout issues which partition critical node transistors within latch cells to minimize multiple node SEU effects. However, these same technologies are ineffective at the sub 100 nm process nodes. Linear energy transfer (LET) is a measure of the energy transferred to material as an ionizing particle travels through it. Typically, this measure is used to quantify the effects of ionizing radiation on electronic devices. Recent 90 nm LET values have been reported near 5 with onset values near 0.5. NASA determines that an LET around 40 is acceptable for flight electronics to be essentially immune to single event upsets. LET values less than 5 represent a serious problem for space flight electronics.
Transistor spacing is a serious issue, but there is another problem that has gone unnoticed. Conventional RHBD electronics are limited to speeds less than 500 MHz, regardless of transistor spacing. The fact which determines the final circuit speed is based on the radiation recovery nature of conventional SEU radiation tolerant latches and the data flow between the latches through combinational logic. For example, when a conventional RHBD cell is upset, it is held in a transition state until the particle responsible for the SEU dissipates, which can take a 1 ns or so. After dissipation, a feedback network must activate to force the circuit into a stable state. All of this can take 2 ns or more.
The essential building block of a RHBD circuit is a radiation tolerant storage element, or cell. Conventional RHBD storage electronics tolerate an SEU impact through a cell recovery process where the cell state is restored to the correct value through a network of feedback signals. Such circuits are formally known as asynchronous sequential circuits. Conventional RHBD technology has essentially ignored operational speed and cell recovery because the speed afforded by older fabrication processes is slower than the SEU particle impact and circuit recovery time. For example, a 1 ns SEU recovery time is within delay times associated with elements of a 250 nm circuit design. As a result, designs can essentially wait for the particle effects to dissipate and not suffer a large speed impact. However, a 1 ns delay greatly impacts the operating speeds of modern sub 100 nm processes.
A conventional RHBD SEU tolerant storage cell is achieved through redundancy. Many different cell designs are currently in use, including a SERT cell, a DICE cell, and a Dooley-Berry cell. The SERT cell has advantages over the DICE cell, for example in a SERT cell, no conflicts between PMOS pull down and NMOS pull up circuits can occur during an SEU. Further, good radiation results have been reported with the SERT cell used in numerous chip designs. The operation of the SERT cell, the DICE cell, and the Dooley-Barry cell are described herein to demonstrate problems with SEU events in speed applications.
FIG. 1 illustrates a schematic diagram of an exemplary SERT cell. The SERT cell, or SERT latch cell, is modeled as an asynchronous sequential circuit with two stable states. A stable state is a state that is stable and does not transition unless an external event occurs. An unstable state transitions to another state due to internal feedback. An asynchronous sequential circuit is a finite state machine which provides an output based on the current inputs and past inputs. In other words, such circuits have memory. Memory is achieved through feedback signals known as internal state variables typically depicted with a symbol yi. An asynchronous sequential circuit can be completely defined in terms of a state table. In the example SERT cell shown in FIG. 1, there are four output terminals, or nodes, Y0, Y1, Y2, Y3, and there are four feedbacks from the nodes, which are referred to as y0, y1, y2, y3. An analysis of the SERT cell is illustrated in a state transition table shown in FIG. 2. The inputs for each of the feedbacks y0 and y1 are shown on the horizontal line above the chart. The inputs for each of the feedbacks y2 and y3 are shown in the vertical line to the left of the chart. The resulting state, or next state, for each of the four nodes Y0, Y1, Y2 and Y3, are shown in each corresponding box in the chart. The variables Y0, Y1, Y2, Y3 can assume binary values (0 and 1). An entry of Z in the chart represents a high impedance condition. The stable states (normal operation state) are 0101 and 1010 because at these internal states the SERT cell retains its state at the output nodes. In normal operation, the circuit transitions between these two states.
The next state equations for the SERT cell are defined by:Y0=y1y3(0)+y1′(1)Y1=y0y2(0)+y2′(1)Y2=y1y3(0)+y3′(1)Y3=y0y2(0)+y0′(1)  (1)The next state variables are noted as Yi and the present state variables, also referred to as the internal state variables, are noted as yi, as per standard asynchronous sequential circuit terminology. The next state defines the state the circuit will assume and are defined in terms of next state variables. In the case of the SERT cell shown in FIG. 1, the next state variables correspond to the nodes Y0, Y1, Y2, Y3 and the present state variables correspond to the feedback variables y0, y1, y2, y3. A variable can assume binary values (0 and 1) and as logic variables can be represented as uncomplemented or complemented variables. A complemented variable, such as yi′ is the inverse of the variable yi. If yi=1, then yi′=0, and vice versa. In general, a pass logic expression Y=A(0)+B(1) means that when A is 1 then a 0 is passed to Y; if B=1, a 1 is passed to Y. As applied to the next state equation (1), the first term on the right hand side of the first equation, y1y3(0), indicates the conditions that will cause Y0 to be driven to the 0 state. In this case Y0 is driven to 0 when both y1 and y3 are high, which corresponds to turning on the two NMOS transistors below node Y0 in FIG. 1 since a NMOS transistor turns on when the gate signal is a logic 1. The second term on the right hand side of the first equation, y1′(1), indicates the conditions that will cause Y0 to be driven to the 1 state. In this case Y0 is driven to 1 when y1 is low, which corresponds to turning on the PMOS transistor above the node Y0 in FIG. 1 since a PMOS transistor turns on when the gate signal is a logic 0. It is impossible to drive Y0 to the 1 and 0 states simultaneously, so node Y0 is free of conflicts. However, if y1 is high and y3 is low then Y0 is not driven and is left in a high impedance state, holding its previous logic level by virtue of the capacitance on this node. The remaining next state equations (1) are similarly interpreted.
Referring to FIG. 2, the cross-hatched and shaded entries denote the stable states. Response to an SEU can be determined from the state transition table. For example, suppose the circuit is in state 0101 and an SEU affects state variable Y2 forcing this node to transition from a 0 to 1 (upset the PMOS device above node Y2). As a result, the circuit enters state 0111 which corresponds to a next state entry of 0Z01, as shown in FIG. 2. In response, the next state action of the circuit drives only Y2 back to a 0, leaving all other state variables at the same value, such that as soon as the SEU event dissipates, the circuit returns to the state 0101, illustrating correct SEU tolerant action. Detailed transition discussions and background information are described in the paper titled “Radiation Hardening by Design” by Gambles et al.
It is possible for the SERT cell to enter numerous states as a result of an SEU. For example, if the SERT cell is in state 0101 and an error occurs on Y3 (state transitions from 1 to 0), this forces the SERT cell to state 0100. As shown in FIG. 2, the state 0100 has a next state entry Z111. With a present state y0=0 and next state=Z, no state change on Y0 is being forced, hence y0 will remain 0. Y1 and y1 are both 1, so there is no change in y1 which will remain 1. With y2=0 and Y2=1, y2 will assume 1. Since Y3 is upset to a 1 from the present state y3=0 by the SEU (assuming the electronics is faster than the time for the SEU to dissipate). Accordingly, with the next state entry Z111, the next state will be 0110. The state 0110 has a next state entry of ZZ11. The SERT cell remains in next state 0110 until the SEU dissipates (state of Y3 returns to 1) after which the SERT cell transitions to state 0111 and then immediately returns to stable state 0101. The recovery time from an SEU requires three circuit transitions, the transition from the state 0100 after the initial SEU event to the next state 0110, the transition from the next state 0110 to the state 0111 after the SEU dissipates, and the transition from the state 0111 to the stable state 0101. The recovery time is determined by the switching time of the electronics and the time for the SEU to dissipate. The table in FIG. 3 includes the same values as in FIG. 2 and the table identifies all the states the circuit can assume as a result of an SEU event. The cross-hatched states denote intermediate states associated with an initial stable state 0101 and the shaded states denote intermediate states associated with an initial state 1010. These same states are the states which the circuit can assume in recovering from an SEU, referred to as transient transition path states. The cross-hatched states in FIG. 3 are the transient transition states corresponding to the initial stable state 0101. The shaded states in FIG. 3 are the transient transition states corresponding to the initial stable state 1010.
As previously indicated, conventional RHBD electronics are speed limited. The speed limitation problem and conventional solution are further described below in the context of the SERT cell. A similar discussion can be applied to other types of cells used in conventional RHBD electronics, such as the DICE cell or the Dooley-Barry cell which are described below. Let the SERT cell have two outputs, Q1 and Q2. In the SERT cell, it is assumed the circuit is in a stable state (in this case either 0101 or 1010 as shown in FIG. 2) to produce a correct output. False data can be clocked out of the SERT cell if the circuit is in an SEU recovery transition state. Suppose y3 and y2 form the SERT cell outputs Q1=y3 and Q2=y2. If the stable state is 0101 and an SEU event occurs forcing the circuit momentarily into state 0100, as in the previous example, then the output Q1 (y3) and the output Q2 (y2) assume false values as the circuit recovers along the transient transition states, the cross-hatched states in FIG. 3. FIG. 4 illustrates the false output values Q1 and Q2 that can propagate if the circuit output is clocked during recovery. If a data latching clock pulse occurs between the dotted lines, a false value can be output. As shown in FIG. 4, the correct value of Q1 should be 1 and Q2 should be 0. One or both outputs are in error between the dotted lines. An output clocked into the next stage would have a false value. It is necessary for the circuit to “recover” which takes time. Clocking too fast produces false outputs. To be correct, clocking has to be slowed, which is a speed limiting problem. The conventional solution to this speed limiting problem assumes the circuit has fully recovered from an SEU event, which is a function of the time for the SEU to dissipate. A 1 ns SEU event can produce many false output values for a 1 GHz clock. While the SERT cell is used to illustrate problems with conventional RHBD circuits, these same problems exist with the other RHBD cells, including the popular DICE cell. The DICE cell has additional design problems relative to proper sizing of transistors over all the process corners and appears to not have the same degree of tolerance as the SERT cell. Moreover, LET problems have been shown for the DICE cell at the 90 nm node. Regardless, the speed problem exists.
Following is a discussion of other self recovering latches, namely the DICE cell and the Dooley-Barry cell. FIG. 5 illustrates a schematic diagram of an exemplary Dooley-Barry cell. The Dooley-Barry cell, or Dooley-Barry latch cell, is modeled as an asynchronous sequential circuit with two stable states. The state transition table for the Dooley-Barry cell is shown in FIG. 6. The stable states for the Dooley-Barry cell are 0101 and 1010. The next state entries are assigned such that every state adjacent to the stable state has the same next state entry as the stable state. In FIG. 6, the cross-hatched states are the transient transitions to the stable state 0101, and the shaded states are the transient transitions to the stable state 1010 such that when an SEU forces one state variable to transition, the circuit returns to the stable state.
In another configuration of a conventional fault tolerant circuit, the DICE cell is used for the self recovering latch. FIG. 7 illustrates a schematic diagram of an exemplary DICE cell. The DICE cell, or DICE latch cell, is modeled as an asynchronous sequential circuit with two stable states. The state transition table for the DICE cell is shown in FIG. 8. The stable states for the DICE cell are 0101 and 1010. It is assumed that all conflicts between NMOS and PMOS are resolved to 0. For example, the NMOS pull down is stronger than the PMOS pull up. The state transition table would be different if the conflicts resolve differently. Under the assumed condition, the cross-hatched states shown in FIG. 8 are SEU transient transition states associated with the stable state 0101, and the shaded states are SEU transient transition states associated with the stable state 1010.